WE DID IT!!!!

let me see what time is it? 3 o'clock in the morning!

yes sir! and we've just almost completed our DILO project!!!

well, almost 70% i think since tomorrow morning we have to go the computer lab to complete the last part of the project which is to translate from altera design(circuit design) into VHDL code which are programming code. basically we have to turn circuit into words to get timing diagram which are the line line thingie that you see...ermm wait..where do you see it in your everyday life? hurrm.......its okla, here's a picture of what timing diagram is...

i dont know if this is a normal thing you see in life but for me, us(engineering students) sooo normal. anyhow, back to our progress, at first the circuit looked like this!

(like the previous post)

however after 6 hours of researching through the net, getting better understanding of the function for each multiplexer,encoder,logic gates, connections, blablablabla(all the techincal stuff)

we finally made it! though not 100% correct since the output didnt turned out the way we want it but hey at least there's an output !! i know i know but hey at least we have something than nothing right? at least we've tried our best and didnt surrender and whine(lalalalala~~)

and thus, after hours and hours of troubleshooting, our final circuit wasssss

much less complicated than the first one, instead of magnitude comparator, we changed it into multiplexer to act as the comparator and decides which algorithmic operations to be done!

i would like to thank NINA MIERA AND SYAH for their time and effort in accomplishing tonight's goal! yes! just now this thing is done...now all that is left for us to sleep and sleep and went to ITMS(computer lab) to get the VHDL codes done with! and ohya..meeting with the other guy......no more comment. enough said. berdosa lagi kang.

funny story, while we were googling images of 6 signed bit adder/subtrator..guess whose picture we found?

i know! even monkeys are interested in building circuits! they have a guy for signed bit adder/sub tractor! hahahaha

okay...major super duper tired sleepy...out peeps!